COMMENT ⊗   VALID 00002 PAGES
C REC  PAGE   DESCRIPTION
C00001 00001
C00002 00002	User programming differences between the KL10 and the KA10.
C00015 ENDMK
C⊗;
User programming differences between the KL10 and the KA10.
Including some information pertaining to the 8.00 series operating
system.

							6/22/76 REG

Preliminary information.   For further details, consult REG or JBR.

AOBJN
KA10 adds 1,,1 to the AC.  The KL does the same, but suppresses the
carry out of bit 18.  That is, if AC contains X,,-1 then on the KA
the result of AOBJN is X+2,,0 and on the KL the result is X+1,,0.

Byte pointers
If the right half of a byte pointer is -1, the KA10 incrementing the
word address will produce a carry into the index field (the result of
an ILDB or IDPB in this circumstance is unpredictable).  On the KL10,
carry out of bit 18 is suppressed.

BLT
On the KA10 the AC of a BLT instruction is unpredictably changed by
the BLT.  On the KL10, before any data is moved, the quantity <last
source address+1>,,<last destination address+1> is stored in the BLT
AC.  If the BLT AC is stored by the BLT (i.e., as a destination) then
it ought to be the last destination location, otherwise, effects of
interrupts may clobber the BLT AC.

Processor identification
The following code will distinguish between a PDP-6, KA10, KI10 and KL10,
in case you need to make this distinction in some program:

	JFCL	17,.+1			;CLEAR ALL PC FLAGS
	JRST	.+1			;TEST FOR PC CHANGE FLAG
	JFCL	1,PDP6			;ONLY PDP-6 PROCESSOR HAS PC CHANGE FLAG
	MOVNI	AC,1			;TEST FOR CARRY OUT OF BIT 18 IN AOBJN
	AOBJN	AC,.+1
	JUMPN	AC,KA10			;KA10 CARRIES ACROSS HALFWORDS
	MOVEI	AC,0			;ON A 1 WORD BLT, THE KI10 WON'T
	BLT	AC,0			;CHANGE THE BLT AC.
	JUMPE	AC,KI10			;IF BLT AC IS STILL ZERO, THIS IS A KI
KL10:

JRST 3, which sometimes appears in spacewar modules, is illegal.
Instead, use JRST 2, and set 10000,,0 in the word being indirected
through.

CONSZ APR,40 and CONSO APR,40 to distinguish between processors
should NOT be used.  Instead, locations 326 (SKIPP1) and 327 (SKIPP2)
contain instructions, which when executed from a spacewar module,
will skip if executed on P1 or skip if executed on P2.  The
instructions should be read into your core image by a PEEK UUO or
somesuch executed at user level (prior to starting your spacewar
module).

The KA10 and PDP-6 FIX instruction, opcode 247 on the KA (and 120-127
and 247 on the PDP-6), does not exist in the KL10.  It will, however,
trap to the monitor which will simulate the effect of the old FIX
instruction.  This simulation may readily be expected to run 50 to
200 times slower than the KA10 version.  It's strongly recommended
that the new KL10 FIX instruction (mnemonic KIFIX in FAIL) be used
instead.  (KIFIX is different from KAFIX.  See below.)

The KA10 long mode floating point instructions (FADL, FSBL, FMPL,
FDVL) and two other floating point instructions UFA and DFN are not
implemented in our KL10's microcode.  These instructions will trap as
UUOs and be simulated by the monitor, running 50 to 200 times slower
than the KA10 versions.  If your program uses these to implement KA10
style double precision floating point, then you are strongly advised
to convert to KL10 hardware double precision format.

UUOs from spacewar mode on the KL10 will reference the spacewar level
accumulators (instead of the user mode accumulators).

Spacewar no longer runs PI in progress on PI channel 7.  Instead it
runs at user level (i.e., not PI in progress anywhere) and channel
7 activity is curtailed except for the spacewar timeout function.

Proprietors of programs that do disk I/O in buffered mode should
consider increasing the number of buffers.  Reasonable choices for
the number of buffers are 19, 10, 7, and 5.  In general, your program
will be able to process data 5 times faster, so that minimizing the
number of disk operations needed by you program will decrease its
overall running time (but not its CPU time) and decrease the disk
bottleneck.  There is no advantage to having more than 19 buffers per
channel.  If your program is largely compute bound, increasing the
buffer size won't help very much.  The disadvantage to having more
buffers is that it increases the total core requirement of the job.

KL10 New instructions: [Note that if you use these instructions, your
program can't be run on the KA10.  If we roll back, you get to
rewrite your program.  The safest thing to do is to wait until the
KL10 is solid, or write programs that figure out which CPU is up, and
execute only appropriate instructions.]

Adjust byte pointer
	IBP AC,E If the AC field of an IBP instruction is not zero,
then AC contains the number of times to increment the byte pointer
addressed by E.  The incremented byte pointer is returned in AC with
contents of E unchanged.  The "increment" may be negative.  NOTE:
This instruction does not always produce the same result as an
iterated IBP.  The difference is that the same byte alignment that is
present in C(E) is preserved by Adjust Byte pointer (if an IBP
crosses a word boundary the bytes become left adjusted in a word).

Example of the difference:
	MOVEI AC,1 		;(AC ≠ 0)
	IBP AC,[000700,,0] 	;result (in AC) is 340700,,1
				;000700 points to right adjusted
				;7 bit bytes as does 340700

	MOVE AC,[000700,,0]
	MOVEM AC,TEMP
	IBP TEMP		;result (in TEMP) is 350700,,1
				;350700 points to left adjusted bytes

ADJSP AC,E
	Adjust stack pointer.  E,,E is added to AC (carry out of bit
18 is suppressed).  If the sign of AC changes, a PDLOV trap results.
E may be negative.

Double precision integer arithmetic.  Operands are 70 bits and a sign
bit (bit 0 of low order word is ignored).  This is the same integer
format that is produced by MUL.

In the descriptions that follow, "AC+1", "AC+2", and "AC+3" are all meant
to be taken modulo 20 (octal).

DADD AC,E
		C(AC, AC+1) ← C(AC, AC+1) + C(E, E+1)

DSUB AC,E
		C(AC, AC+1) ← C(AC, AC+1) - C(E, E+1)

DMUL AC,E
		C(AC, AC+1, AC+2, AC+3) ← C(AC, AC+1) * C(E, E+1)

DDIV AC,E
		C(AC, AC+1)   ← Quotient  of C(AC, AC+1, AC+2, AC+3) / C(E, E+1)
		C(AC+2, AC+3) ← Remainder of C(AC, AC+1, AC+2, AC+3) / C(E, E+1)

EXTEND	
	USERS ARE ADVISED TO AVOID "EXTEND".
	Various conversion and string manipulation operations are
available.  Details will be forthcoming when we decide what subset of
the DEC EXTEND instruction to implement.  We're short on microcode
space so some of the DEC supplied EXTEND code may have to be
sacrificed.  The existing microcode for EXTEND has not been extensively
tested; it may be buggy, especially with respect to interrupts.

DMOVE AC,E
		C(AC, AC+1) ← C(E, E+1)

DMOVN AC,E
		C(AC, AC+1) ← -C(E, E+1)

DMOVEM AC,E
		C(E, E+1) ← C(AC, AC+1)

DMOVNM AC,E
		C(E, E+1) ← -C(AC, AC+1)

DFAD AC,E
		C(AC, AC+1) ← C(AC, AC+1) + C(E, E+1)

DFSB AC,E
		C(AC, AC+1) ← C(AC, AC+1) - C(E, E+1)

DFMP AC,E
		C(AC, AC+1) ← C(AC, AC+1) * C(E, E+1)

DFDV AC,E
		C(AC, AC+1) ← C(AC, AC+1) / C(E, E+1)

KIFIX AC,E
	AC ← contents of E (a floating point number) converted to integer format.
Truncation of the fraction moves the result closer to zero.  (E.g., 1.9 is
truncated to 1, -1.9 is truncated to -1).  (Fortran style IFIX)

FIXR AC,E
	AC ← contents of E (a floating point number) converted to integer format.
Fractional part is rounded by adding 0.5 and then truncating towards -∞.
(E.g., 1.5 is rounded to 2, -1.5 is rounded to -1, -1.6 is rounded to -2)
(Algol style real to integer conversion).

FLTR AC,E
	AC ← contents of E (an integer) converted (by rounding, if needed) to
floating point format.

KL10 PC flag bit assignments:

 0	AR OV
 1	AR CRY0						
 2	AR CRY1
 3	FOV
 4	FPD (First Part Done, essentially the same as BIS)
 5	User
 6	User In-Out
 7	Public  (Setting this bit causes a proprietary violation)
 8	Address Failure Inhibit
 9	Trap 2
10	Trap 1
11	FXU
12	DCK
13-17	Zero
18-35	PC

All bare machine programs will have to be changed for the KL10.
Interfaces to CTY, IOP, DC (and thus MTA, DTA) have been changed.
Any programs that reference these from IOT user mode or spacewar mode
are now incorrect.